Comparative Study of Total Ionizing Dose Effects in sub-20 nm Bulk Silicon FinFET Technology at 110 K and 290 K

Abstract: This article investigates the synergistic effects of cryogenic temperatures and radiation exposure on aerospace components. Test chips were fabricated using a sub-20 nm bulk silicon FinFET process, primarily comprisingring oscillators and bandgap reference (BGR) circuits that incorporate parasitic vertical PNP bipolar transistors. Radiation experiments employed a 60Co γ-ray source with a dose rate of 200 rad(Si)/s and a total dose of 1 Mrad(Si), comparing two temperature conditions: 110 K and 290 K. Following a 1 Mrad(Si) irradiation, chip #1 maintained at 290 K exhibited a 113% increase in leakage current relative to its fresh state. In contrast, chips #2 and #3, both irradiated at 110 K, demonstrated substantially larger increases in leakage current, reaching 7133% and 4248%, respectively. Post-irradiation measurements at 290 K indicated leakage current increases of 93%, 9336%, and 5677% for chips #1, #2, and #3, respectively. All ring oscillator frequency variations remained below 0.5%, confirming the negligible Total Ionizing Dose (TID) impact on threshold voltage. Following cryogenic irradiation, an increase of 37 units in the BGR’s temperature code was observed for chip #2, which is considerably higher compared to the 15-unit increase noted for chip #1 after room-temperature irradiation. Both leakage current and temperature codes demonstrated a clear cryogenic-temperature-enhanced damage effect. By analyzing the role of temperature on each stage of the TID effect, we found that cryogenic temperatures primarily impact two processes: hole transport and interface trap formation. The underlying mechanism involves significantly reduced hole mobility and suppressed interface trap formation at cryogenic temperatures, resulting in a substantially larger net positive charge accumulation in the Shallow Trench Isolation(STI) compared to that at room temperature. Three-dimensional Technology Computer-Aided Design (TCAD) modeling and simulation confirmed that under 110 K, the inversion layer area at the channel bottom was larger and the electron density was higher than at 290 K. These findings provide important insights for the design and research of FinFET integrated circuits for aerospace applications.